Analysis focusing on density of state-of-the-art products allows development of an envelope function as an indicator of the fabrication capabilities and techniques. Recently, a new definition of transistor density has been suggested, and we propose to reexamine processor evolution by examining growth in the number of transistors per unit area, accounting for changes in chip size. However, increases in transistor count may be coupled with increases in chip size (die area) that is, more transistors can be added to a processor by increasing its size (area or volume). Most research has accepted Moore’s assumption of the exponential doubling of computer processor complexity, defined as the number of units per chip. These descriptive models do not attempt to explain the underlying mechanisms of increasing technological performance per se, though they can give insight into evolution of the complex system. Logistic component analysis, as well as rate analysis, of empirical data may be able to discriminate the timing of important technical improvements directly from the data, elucidating the main trends in the miniaturization of transistors. Technological evolution frequently displays these more complex kinetics with a tendency to saturate because of constraining factors, and this pattern is also reported for semiconductor performance. It is clear that technological evolution, hypothesized here to include transistor miniaturization, is discontinuous and that new designs and processes are distributed unevenly through time in “innovation waves”. The hypothesis of linked S-curves has been put forth by Foster and Christensen. Indeed, many systems of increasing complexity and information exhibit discontinuous multiphasic trends. Technological progress has also been identified with a quasi-fractal wavelet process conceptualizing growth as an agglomeration of distinct subprocesses. The ability of the simple logistic model to describe this process may be due to intrinsic technological and physical factors, as well as economic forces constraining unfettered increase in complexity. Further, these patterns have been recognized in innovation generally, including technology life-cycles and learning systems.

S-curves can describe the growth of technological performance. Sigmoidal models have been shown to be compatible with technological evolution, even in the context of Moore’s Law of transistor performance, giving rise to decreasing growth rates as a technology matures. These observations are generally referred to as “Moore’s Law”, a benchmark that has become a largely undisputed, though perhaps misunderstood, rule for the microprocessor industry. The observed trend slowed from a doubling in the number of components per chip every year to doubling every two years, with an intermediate doubling time of 18 months. It has been observed that the number of semiconductor components on a silicon chip increases exponentially and is expected to stop growing only when uncertain limits have been reached. The six waves of transistor density increase account for and give insight into the underlying processes driving advances in processor manufacturing and point to future limits that might be overcome. During each stage, transistor density increased at least tenfold within approximately six years, followed by at least three years with negligible growth rates. Density of Intel processors between 19 are consistent with a biphasic sigmoidal curve with characteristic times of 9.5 years. Growth in the number of transistors per unit area, or chip density, allows examination of the evolution with a single measure. We note that the increase encompasses two related phenomena, integration of larger numbers of transistors and transistor miniaturization. Analysts have debated whether simple exponential growth describes the dynamics of computer processor evolution. Gordon Moore famously observed that the number of transistors in state-of-the-art integrated circuits (units per chip) increases exponentially, doubling every 12–24 months.

Cpu transistor function